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Network on Chip Architectures Scientia Research LibraryJournal of Engineering and Technology Research2348 - 0424201645 [1]*S.Sariga,[2] C.Nandagopal Pagr No. 1-9 1 As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current Systemon-Chip (SoC) implementations where only a limited number of functional units can be supported. Networkon-Chip (NoC) architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. Moreover, as technology scales down in geometry and chips scale up in complexity, NoC become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Key words: Network on Chip, Globally AsynchronousLocally Synchronous (GALS), ANOC, Time Division Multiplexed NOC, QNOC, Quality of Service (QoS) http://www.scientiaresearchlibrary.com/archive-abs.php?arc=481http://www.scientiaresearchlibrary.com/archive/JETR-2016-4-5-121-1-9.pdf